The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) processes. The FEOL process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL process may include gate and terminal contact formation. The BEOL processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the FEOL and MOL processes. Successful fabrication and qualification of modern semiconductor chip products involves an interplay between the materials and the processes employed. In particular, the formation of conductive material plating for passive on glass (POG) devices in BEOL processes is an increasingly challenging part of the process flow.
When fabricating high density capacitors such as metal-oxide-metal (MOM) capacitors or decoupling capacitors, a challenge that remains is saving chip area and boosting chip performance while limiting the number of capacitors. The number of capacitors for high performance devices continually increases due to the scaling of integrated circuits. Therefore, being able to efficiently achieve high capacitance levels with a limited number of high density capacitors is a concern.